1. Field of the Invention
The present invention relates to a semiconductor fabrication technology; and more particularly, to a method for forming a gate of a semiconductor device.
2. Description of Related Art
As integration density of semiconductor devices is increasing, a channel length of a transistor is reduced and concentrations of a source and a drain are gradually increased. Thus, severe interference between the source and the drain causes a short channel effect that reduces a threshold voltage and increases leakage current. In order to suppress the short channel effect, intensive researches have been made on a recess gate type transistor and a triple gate type transistor among transistors with polyhedral channel.
According to a method for forming a recess gate type transistor, a substrate of a channel region is etched to a certain depth to form a trench, and a gate insulation layer is formed along an inner surface of the trench. Then, a gate is formed on the gate insulation layer to fill the trench. In such a structure, electrical properties are remarkably improved because interference between a source and a drain is suppressed.
However, in the method for forming the recess gate type transistor, since the substrate is etched by a plasma etching process, a region for channel is damaged by plasma, causing crystal defects such as stacking fault. Thus, interface trap density is increased. Furthermore, surface roughness is degraded due to characteristic of plasma etching. Moreover, when a trench is formed by etching the substrate, an upper edge portion is formed sharply and an electric field is concentrated on the sharp upper edge portion, resulting in degradation in characteristic and reliability of the device.
Next, problems of the triple gate type transistor will be described.
FIG. 1 is a perspective view for explaining a typical triple gate type transistor.
Referring to FIG. 1, the typical triple gate type transistor has channels on three surfaces: two sides (sidewalks) and an upper surface. Since the two sides are formed as the channel, a much larger current can be obtained even though a device has the same size. In FIG. 1, reference symbols “G”, “D” and “S” represent a gate electrode, a drain region, and a source region, respectively.
FIG. 2 is a perspective view explaining problems of the typical triple gate type transistor.
Referring to FIG. 2, a substrate is etched in order for using sides as a channel. At this point, a plasma etching process is usually used.
Such a plasma etching process has three problems as follows.
First, crystal defect is caused by plasma damage. If crystal defect caused by plasma damage occurs in the side A to be used as a channel, device characteristics are degraded. In particular, the reliability of the device is degraded.
Second, the use of the plasma etching process degrades surface roughness such as striation that is inevitably formed in the side A during the plasma etching process. The surface roughness of the side A reduces carrier mobility, thus degrading device characteristic.
Third, electric field concentration occurs in the upper edge portion B. When the radius of curvature of the edge portion B is small, an electric field applied to a gate oxide layer increases. Thus, failure of the gate oxide layer is caused, or the lifespan of the gate oxide layer is reduced. As illustrated in FIG. 3, when the radius of curvature is 7 nm, a higher electric field is applied to the edge portion than a flat portion by approximately 9%.